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dc.contributor.authorFahem Z
dc.contributor.authorCsaba G
dc.contributor.authorErlen C
dc.contributor.authorLugli P
dc.contributor.authorWeber W
dc.contributor.authorGeelhaar L
dc.contributor.authorRiechert H
dc.contributor.editor
dc.date.accessioned2019-04-29T09:46:46Z
dc.date.available2019-04-29T09:46:46Z
dc.date.issued2008
dc.identifier.issn1862-6351
dc.identifier.urihttp://dx.doi.org/10.1002/pssc.200776578
dc.identifier.urihttp://onlinelibrary.wiley.com/doi/10.1002/pssc.200776578/abstract
dc.identifier.urihttp://hdl.handle.net/10863/9550
dc.description.abstractWe present a combined experimental and theoretical analysis of the transport properties of silicon nanowire (NW) transistors. The NWs are grown by catalytic chemical vapour deposition and are later deposited on pre-patterned oxidized silicon substrates that provide the device source and drain electrodes. A back gate configuration is used for our study. Through a controlled nickel diffusion, parts of the nominally undoped NWs are turned into nickel suicide NWs, thus providing a direct metallic nanolead to the semiconducting wire. The transistors obtained with NWs of 10-30 nm diameters display p-type behaviour, current densities up to 0.8 MA/cm, and on/off current ratios of up to 10. The subthreshold characteristics show a strong hysteresis. The simulation based on a drift-diffusion approach indicates that traps at the interface between the NWs and SiO are responsible for such behaviour. © 2008 WILEY-VCH Verlag GmbH & Co. KGaA.en_US
dc.languageEnglish
dc.language.isoenen_US
dc.relation
dc.rights
dc.titleAnalysis of the hysteretic behavior of silicon nanowire transistorsen_US
dc.typeArticleen_US
dc.date.updated2019-04-28T03:02:23Z
dc.publication.title
dc.language.isiEN-GB
dc.journal.titlePhysica status solidi. C, Current topics in solid state physics
dc.description.fulltextreserveden_US


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