Analysis of the hysteretic behavior of silicon nanowire transistors
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We present a combined experimental and theoretical analysis of the transport properties of silicon nanowire (NW) transistors. The NWs are grown by catalytic chemical vapour deposition and are later deposited on pre-patterned oxidized silicon substrates that provide the device source and drain electrodes. A back gate configuration is used for our study. Through a controlled nickel diffusion, parts of the nominally undoped NWs are turned into nickel suicide NWs, thus providing a direct metallic nanolead to the semiconducting wire. The transistors obtained with NWs of 10-30 nm diameters display p-type behaviour, current densities up to 0.8 MA/cm, and on/off current ratios of up to 10. The subthreshold characteristics show a strong hysteresis. The simulation based on a drift-diffusion approach indicates that traps at the interface between the NWs and SiO are responsible for such behaviour. © 2008 WILEY-VCH Verlag GmbH & Co. KGaA.