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dc.contributor.authorNiemier M
dc.contributor.authorCsaba G
dc.contributor.authorDingier A
dc.contributor.authorHu X
dc.contributor.authorPorod W
dc.contributor.authorJu X
dc.contributor.authorBecherer M
dc.contributor.authorSchmitt-Landsiedel D
dc.contributor.authorLugli P
dc.contributor.editor
dc.date.accessioned2018-09-03T08:13:56Z
dc.date.available2018-09-03T08:13:56Z
dc.date.issued2012
dc.identifier.isbn978-1-4673-0287-6
dc.identifier.urihttp://dx.doi.org/10.1109/CNNA.2012.6331413
dc.identifier.urihttp://ieeexplore.ieee.org/document/6331413/
dc.identifier.urihttp://hdl.handle.net/10863/5945
dc.description.abstractWe present the design and simulation of information processing hardware that is comprised of single domain, Co/Pt magnets (i.e., out-of-plane nanomagnet logic - or oNML). We first describe the design and evaluation of oNML hardware that can identify instances of a preprogrammed bit sequence in streaming data. Systolic arrays (that process information using Boolean logic gates) are employed as a system-level architecture which can (i) mitigate less desirable features of the oNML device architecture (nearest neighbor dataflow and longer device switching times when compared to a CMOS transistor), and (ii) exploit unique features of the device architecture (non-volatility and inherently pipelined logic with no overhead). We conclude the paper with a discussion as to how oNML might be employed for non-Boolean information processing. A simple image processing function is used as an initial case study. © 2012 IEEE.en_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.rights
dc.titleBoolean and non-Boolean nearest neighbor architectures for out-of-plane nanomagnet logicen_US
dc.typeBook chapteren_US
dc.date.updated2018-09-03T07:02:46Z
dc.publication.title2012 13th International Workshop on Cellular Nanoscale Networks and Their Applications (CNNA 2012) : Turin, Italy, 29 - 31 August 2012
dc.language.isiEN-GB
dc.description.fulltextreserveden_US


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