Modeling and high-frequency simulation of InAs nanowires
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SubjectSimulation; Wrap gate; Trap states; Nanowire (NW); InAs; Field-effect transistor (FET); Cutoff frequency
In this paper, we have investigated the transport in InAs nanowire-based wrap gate field-effect transistors and their high-frequency performance. State-of-the-art InAs devices reveal excellent dc performance in terms of transconductance, subthreshold slope, and saturation behavior. Only, very recently high-frequency measurements have been performed on these devices, demonstrating that they can operate well in the gigahertz range. However, their intrinsic high-frequency performance and the limiting mechanism in reaching the optimal limit have not been fully understood yet. One of the main reasons lies in the technological difficulties in contacting the nanometer devices and in the parasitic elements that arise from this imperfect measurement setup. Making use of a sophisticated hydrodynamic simulator, we are able to successfully reproduce the experimental output characteristics over the entire measurement range. Next, we also perform a detailed simulation study of the frequency response for the measured samples, with and without an extrinsic parasitic network. Based on our simulations, we deduce that the intrinsic high-frequency performance of these devices is at least one order of magnitude higher than currently reached today, in terms of maximum oscillation frequency and cutoff frequency, and that the parasitic network is the major limiting factor. Furthermore, we identify the parasitic elements that have the greatest impact on the device performance and we explain their working principles. © 2002-2012 IEEE.
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