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dc.contributor.authorJu X
dc.contributor.authorNiemier M
dc.contributor.authorBecherer M
dc.contributor.authorPorod W
dc.contributor.authorLugli P
dc.contributor.authorCsaba G
dc.contributor.editor
dc.date.accessioned2017-11-20T12:31:50Z
dc.date.available2017-11-20T12:31:50Z
dc.date.issued2013
dc.identifier.issn1536-125X
dc.identifier.urihttp://dx.doi.org/10.1109/TNANO.2013.2253118
dc.identifier.urihttp://ieeexplore.ieee.org/abstract/document/6481449/
dc.identifier.urihttp://hdl.handle.net/10863/3998
dc.description.abstractWe present the design and simulation of systolic information processing hardware that is comprised of single domain, Co/Pt magnets (i.e., out-of-plane nanomagnet logic or oNML). The designed circuit can identify instances of a preprogrammed bit sequence in streaming data. The systolic architecture 1) exploits unique benefits of the oNML device architecture such as nonvolatility and inherently pipelined logic with no memory overhead for holding the bits in the pipeline and 2) mitigates less desirable features of oNML such as nearest neighbor dataflow and longer device switching times when compared to a CMOS transistor. The designed layout is verified and analyzed by micromagnetic simulations. We quantify how the performance and energy of oNML information processing hardware compares to CMOS equivalents and conclude that the initial oNML design (including the overhead of magnetic field generation) is about an order of magnitude more power efficient at essentially iso-performance. © 2002-2012 IEEE.en_US
dc.language.isoenen_US
dc.rights
dc.subjectCo/Pt nanomagnetsen_US
dc.subjectMicromagnetic simulationen_US
dc.subjectSystolic circuitsen_US
dc.subjectNanomagnet logic (NML)en_US
dc.subjectMagnetic logicen_US
dc.titleSystolic pattern matching hardware with out-of-plane nanomagnet logic devicesen_US
dc.typeArticleen_US
dc.date.updated2017-07-31T10:19:06Z
dc.publication.title
dc.language.isiEN-GB
dc.journal.titleIEEE Transactions on Nanotechnology
dc.description.fulltextreserveden_US


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