Relative Gate Placement in Multimodal Thin-Film Transistors for Negligible Impact on DC Characteristics

Conference proceeding

Peer reviewed

A Niaz, E Bestelink, Niko Stephan Münzenrieder and RA Sporea

SID Symposium Digest of Technical Papers: Volume 56, Issue S1, Vol.56(S1), pp.92-92

56

SID Display Week (San Jose, 11/05/2025–16/05/2025)

2025

Handle:

https://hdl.handle.net/10863/50189

Files and links (1)

url

https://doi.org/10.1002/sdtp.18732View

Title: Relative Gate Placement in Multimodal Thin-Film Transistors for Negligible Impact on DC Characteristics
Creators: A Niaz - University of Surrey
E Bestelink - University of Surrey
Niko Stephan Münzenrieder - Free University of Bozen-Bolzano
RA Sporea - University of Surrey
Publication Details: SID Symposium Digest of Technical Papers: Volume 56, Issue S1, Vol.56(S1), pp.92-92
Conference: SID Display Week (San Jose, 11/05/2025–16/05/2025)
Series / Volume: 56
Publisher: Wiley
Number of pages: 1
Identifiers: (UNIBZ)91600432
991007196443801241
Scopus ID: 2-s2.0-105013027880
Academic Unit: Faculty of Engineering
Language: English
Resource Type: Conference proceeding
Author Names String: Niaz A, Bestelink E, Münzenrieder N, Sporea RA

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